A 10-bit 300 MSPS DAC With Variable Gain Based on 28nm Process

This paper presents a variable gain three-channel 10-bit current steering CMOS digital-to-analog converter (DAC) implemented in a standard 28-nm CMOS technology. The DAC achieved variable gain of 0~-5.75 dB with five-bits control words to apply to a wider range of applications. The DAC is segmented as 6+4, where the 4-LSB bits are implemented in binary and the 6-MSB bits are implemented in unary architecture. The spurious free dynamic range (SFDR) of this DAC can be improved by using clipper circuit in the part of switches. The reference voltage of bandgap must be low enough to meet the requirements of bias voltage in the part of voltage changing to current. The circuit is fabricated in 1.8-V analog power supply and 1.05-V digital power supply. For sampling frequencies up to 300MSample/s, the SFDR is better than 64 dB. The measured differential nonlinearity and integral nonlinearity are 0.3 least significant bit (LSB) and 0.4 LSB, respectively.