A BCD Technology with Vertical DMOS

In current BCD technology,outlets of the circuit are led from top surface of the chip.Therefore,buried layers and sink areas are needed to make good contact and device interconnect. These structures reduce the integration of power chips, and introduce additional resistance and parasitic capacitance, and complicate interconnection especially for high voltage interconnection.In this paper,a new BCD technology was proposed. High voltage VDMOS was integrated in this new technology,and it was designed with the Drain contact on the back.This new technology overcomes the disadvantages of the conventional BCD technology.The simulation results shown that for VDMOS,the threshold voltage is 2.5 V and D-S breakdown voltage is 161 V,for NPN and PNP,C-E breakdown voltage is 47.32 V and 32.73 V,βis 39.68 and 9.8 respectively,for NMOS and PMOS,threshold voltage is 0.65 V and -1.16 V respectively,D-S breakdown voltage is 17.37 V and 14.72 V respectively.