A Temper-Resistant Detecting Technique Against Physical Attack

A temper resistant detecting technique applied in high security chips is proposed in this paper.The method utilize the topmost layer to monitor attack behaviors in real time, which prevents the key information stored in circuits from being stolen.An optimized algorithm for generating a random hamilton path of the layout in VLSI circuits is proposed.Using this algorithm, a highly disordered topology with a large area can be generated in a short time.The proposed method can increase the time and cost for the invasive attacks and improve the physical defense ability.