A Design of Fully Integrated Alternating Dual Slope ADC

This paper presents a fully on-chip small area dual slope ADC for biomedical application. Base on the proposed multi-window dividing method, the RC time constant of the integrator is greatly reduced, which helps the ADC to save large amount of area for the on-chip capacitor. The auto-zero technique is applied to reduce the offset of integrator, and dynamic comparator is used to save power. The proposed 10 bit dual slope ADC has a sampling rate of 418S/s at 2 V supply voltage, consuming 18.5 μA current. The proposed dual slope ADC is implemented in 0.35 μm CMOS process occupying an area of 0.16 mm². Matlab simulation results show that the effective number of bits (ENOB) for the ADC is 9.77 bit.