Design of Floorplanning Algorithm in Three-Dimension Integrated Circuit Based on Thermal and Utilization

To address the floorplanning problem in 3D IC design flow, this paper proposes a floorplanning algorithm based on thermal and utilization. Several simulated annealing processes are also used in the design. At last, a modified 3D IC floorplanning design flow is completed. This paper verifies the new algorithm on MCNC benchmark circuits. According to the result, the new algorithm improves the floorplanning utilization above 30% in average as well as decreases peak temperature by about 3%.