Segmented Filtering Circuit for SET Pulse in Flash-based FPGAs

A segmented filtering circuit with delay units and guard gates is proposed to filter SET pulses with different width, considering the range and distribution of SET pulse widths produced in FPGA and the propagation induced pulse broadening. Dividing the widths of SET pulses into several intervals, parallel guard gates with different delay buffers generate corresponding results to different intervals. According to the results, this circuit selects the output in the shortest time, improving the performance on dealing with SET pulses. Simulation results in Fusion family flash-based FPGA indicate that, compared to traditional methods, the segmented filtering circuit can cut the filtering delay of SET pulse in critical path down to 10.42%~49.8%, while power consumption decreasing and no hardware resource increase.