Design and Simulate High Performace ASIP for PLC

The PLC ASIP adpots PLC special instruction set, which is consistent with the character of PLC instructions.The PLC special instruction set can reduce the number of instructions and accelerate the executing speed of PLC program by 32 bit RISC architecture.The designed architecture of the high performance ASIP for PLC adopts harvord bus architecture, the registers adopts bit addressing mode, the bit processor can accelerate bool operation, the function block unit can improve the precision of function block execution, the high performance ASIP for PLC adopts four pipelines to speed up the PLC instruction execution.The systemic functional simulation of the high performance ASIP for PLC has been finished, and the result of simulation is correct after testing.