Design and Implementation of Long Integer Modular Exponentiation Unit of Asymmetric Encryption in Smart Card

In this paper, we design a key-length-configurable modular exponentiation based on CIOS modular multiplication algorithm and Montgomery powering ladder exponentiation algorithm. The long integer modular exponentiation circuit is synthesized by Synopsys Design Compiler under the clock frequency of 50 MHz and SMIC13LL technology at a cost of 16.1k gates and throughput is 10 kb/s and Primetime PX power report shows that the average power consumption of 30 MHz is 2.87 mW, which achieves the requirements of speed, power consumption and circuit area of smart card. The modular multiplication circuit proposed by this thesis achieves high resource utilization rate and smallest "power×area/throughput" in comparison with modular multiplication of systolic array architectures.