An Architecture and VLSI Implementation of Deblocking Filter for AVS HDTV Application

This paper presents a novel Deblocking filter for AVS.It uses dual-port memory which receives reconstruction pixels while calculating the filter result to reduce input to output delay.It achieves high efficiency by improving timming and adopts pipeline structure to increase the frequency.Simulate this module and implement use 0.18 μm, the frequency reaches 200MHz and the circuit costs 18×10³ Gates, supports 1920×1080, 60 frames per second video decoding.