An Approach on Pulse Generation of SET Emulation

This paper presents a technique based on electrical pulse generation with a PLL (Phase Locked Loop),which can produce the smallest pulses whose width is 325 ps.This paper accomplishes the study of SETs propagation in combinational logic in SRAM-based Field Programmable Gate Arrays (FPGAs).Experimental results demonstrate this method is so simple that it can change the output pulse width without the alteration of logic path place and route,and the error rate of the pulse width between the measure results by using oscilloscope and the calculating results by using phase of PLL is less than 3%.