Research and Implementation of Network-on-Chip Interlinkage Structure for Multi-core Cipher Processor

In order to solve the problem that a single-core cipher processor cannot satisfy the high speed cryptographic operations' demand, this paper focused on the network-on-chip architecture and proposed a new architecture based on shared memory for multi-core cipher processor. In the proposed architecture, this paper analyzed the characteristic of cryptographic operations and achieved a DES algorithm mapping. Comparing with the single-core cipher processor, the proposed architecture gets a better parallelism and expansibility, to provide a giant bandwidth and fine grit cryptographic algorithm support. An efficient data interaction mechanism is able to improve the performance of multi-core cipher processor, and achieved a maximum throughput for 426 Gb/s. The performance of the proposed architecture improved about 5.7%~37.5% when compared with the general purpose multi-core processor in achieving cryptographic algorithms.