A 2.8 GHz charge-pump phase locked loop in 90 nm CMOS

In the paper, a charge-pump phase clocked loop with low phase noise in 90nm CMOS, which is used to synthesis two quadrature local oscillator signals, is designed for a UWB transceiver SOC. In the implementation, this paper proposes a method of inserting a transmission gate on the switching link on the phase frequency detector to reduce the dead zone and the influence of the current mismatch. The low division factor and the high frequency reference signal improve the phase noise of the loop. A capacitor array is used to calibrate the voltage controlled oscillator to reduce process variations and the effects of parasitic parameters on the tuning range. After completing the phase-locked loop layout design, the parameters of each module are extracted and post-simulation is performed. The SPECTRE simulation results show that the phase noise of the phase-locked loop is -125dBc/Hz@1MHz, and quadrature signals are produced by the differential 2 divider.