A Configurable Test Circuit of Propagation Delay for Antifuse FPGA

In order to evaluate the performance of the antifuse FPGA and classify the chip speed level, a test method of propagation delay is proposed. Aimed at the characteristics of one time programmable and diverse application requirements for the antifuse FPGA, a novel test circuit is designed, which includes the influencing factors of the propagation delay. The circuit exhibits a variety of configurable capacity, including the test link configuration, the routing length configuration, the fanout value configuration, etc. The performance evaluation solution for the antifuse FPGA is practical and feasible. The results of the circuit simulation and the silicon verification based on the 1.0um CMOS ONO antifuse process show that the test circuit of propagation delay is suitable for the application of antifuse FPGA development.