The Implement of LDPC Decoding Algorithm Based on FPGA Programming in C

In order to obtain the balance of the decoding rate and the hardware consumption, a new method to implement LDPC decoding algorithm is proposed.For the characteristics of the decoding algorithm, this method is based on an up-to-date parallel technique from Impulse C programming to hardware implementation.A decoder for a family of (3, 6) LDPC Codes with a code rate of 0.5 and a block size of 2500 bits is implemented on Xilinx Virtex2 XC2V2000.By performing maximum 10 decoding iterations, the decoder can achieve a maximum bit throughput of 10Mbps.