Design and Implement of a Configurable PWM IP Core With Hardware Trigger Mechanism

A pulse width modulation (PWM) IP core that having the advantages in configuration, instantaneity and applicability is proposed in this paper. Not only does the PWM IP core support hardware trigger and feedback mechanism for enhancing interconnection among IP cores in the System-on-a-Chip (SoC), but it can also offer a practical scheme with resource reuse inside the PWM IP core. Finally, according to comparative and analytical results of simulation and verification, they indicate that PWM IP core can support multiple output modes, and consuming time of hardware trigger is two times less than traditional software trigger's by building environment of simulation, editing excitation of test and using tools of simulation. In conclusion, it can meet needs of different configuration, high instantaneity and efficient applicability for achieving design's aim.