An Effective Architecture for Designing Modulo (2 ⁿ-2 ^p) Multipliers

In this paper,a new architecture is proposed to design modulo (2ⁿ -2^p) multipliers on the condition n ≥ 2 p.When compared with the reference multipliers1, the proposed multiplier reduces both time delay and hardware requirements significantly. The proposed design is very suitable for VLSI implementation. It can be completed in one cycle.