Hardware Architecture for the Montgomery Multiplication Algorithm

In this paper, regular and flexible hardware architecture based on the systolic array for implementing the multiple-word radix-2 Montgomery multiplication algorithm is proposed, and it has been used to implement the algorithm in FPGA for different bit-widths. The architecture successfully limits the critical path of the systolic array to the critical path of the adder in a processing element, without any additional circuits or clock cycles needed. According to the hardware implement results, the proposed architecture has higher frequency, less latency and less area.