VLSI Design of 2D DST Architecture for HEVC

To improve the Intar coding performance, HEVC(High Efficiency Video Coding) is applied to Integer discrete sine transform for the first time. To solve the problem of that the DST algorithm applied to hardware design that can increase circult area and reduce operational speed, a new DST algorithm is proposed based on the characteristics of the DST matrix coefficients. And the special signal multiplier is designed by the new algorithm. To increase operational speed and to reduce circuit area, the circuit adopts the single-port input and output and the combination accumlation method. Using SMIC 0.18 μm technology, the proposed architecture is implemented with the maximum work frequency at 250 MHz and 358 940 μm² circult area. From simulation result, this design is working and can get a streamline circult.