A Design of Multiplier With High-Compress Wallace Tree

This 32×32 multiplier supports both signed and unsigned integer multiplication by an additional sign bit.It adopts the Booth algorithm to reduce the number of partial product and optimize it.The multiplier increases the calculation speed through the Wallace tree with 7:2 compressor and Brent Kung tree.It is designed by verilog language and simulated correctly by Modelsim.The performance parameters are obtained by Synopsys' Design Compiler with SMIC's 0.18μm target library.