Design of ADDLL for 3D-IC Die-to-Die Clock Synchronization

In this paper, an all-digital delay-locked loop (ADDLL) for die-to-die clock synchronization of three-dimensional integrated circuit (3D-IC) is presented. The proposed ADDLL can endure the delay variations between through silicon vias and synchronize the clock signals between vertically stacked dies of the given 3D-IC. In order to solve the harmonic lock problem and widen the operating frequency, the circuit shortened the lock process by the use of variable successive approximation register-controlled scheme. The presented ADDLL is implemented using the TSMC 65 nm CMOS low power technology, and the simulation results show that the highest operating frequency is 833 MHz at the worst case (SS, 125℃, 1.08 V), the lowest operating frequency is 167 MHz at the best case (FF, -40℃, 1.32 V), the longest lock time is 103 cycles of the input clock, and the power consumption is estimated to be 0.8mW@833MHz at the typical case (TT, 25℃, 1.2 V). The area of the ADDLL per die is 0.018 mm².