Design of a high performance ESD power clamp circuit

A novel ESD power clamp circuit is proposed in this paper. A feedback structure is used to extend turn-on time of the circuit under ESD event, and enhance the robustness of the circuit to avoid false triggering during normal power supply. Compared with the traditional structure, the capacitance in the detection circuit is only 20fF, which saves the layout area. The simulation results show that the turn-on time of BIGFET can reach 1μs when ESD is coming. When the 5V/1μs high-speed power supply voltage is powered on, the BIGFET does not turn on accidentally. Therefore, the ESD power clamp circuit designed in this paper can be widely used in various high-speed circuits.