A 4T Dual Replica-Bitline Delay Technique Forprocess- Variation-Tolerant Low Voltage SRAM Sense Amplifier Timing

A 4T dual replica-bitline delay technique for reducing access time by suppressing enable timing variation of a sense amplifier was developed. This strategy suppresses the timing variation by adding one another replica-bitline and introducing a novel 4T replica cell which has 4 MOS transistors. At the supply voltage of 0.6V, the simulation results show that the standard deviation of the SA-enable timing and cycle time with the proposed technique is 30.8% and 12.3% smaller than that with a conventional RBL technique in Taiwan Semiconductor Manufacturing Company 65-nm CMOS technology respectively. Moreover, for the MOS number of 4T replica cell is 1/3 smaller than conventional replica cell, it will reduce the overall area overhead.