Architecture of a High Performance SIMD Multiplication Array

This paper presents a 64-bit fixed-point SIMD multiplication array.This array has capable of supporting one 64 × 64,four 32 × 32 or sixteen 16 × 16 bit signed/unsigned.The component is used more efficient with multiplication cell array.Implement all above function with a small increase in delay and area.An algorithmof"overflow compensate" is introduced,which solve the overflow judgment in fixed-point complex multiplication.The synthesize result shows that the multiplication reduces the 64 bit multiplication's critical path by 3.65%,reduces the area by 3.92% and increases the power consumption by 5.71%.