Design and Optimization of the 108-bit Leading Zero Counter's Circuit

This paper adopts 2-bit parallel packet to count respectively, 108 leading zero counter circuit design uses the structure which is two binary tree. The timing that 108-bit leading zero counter using 2-bit packet which is analyzed by PT is 0.17, and the timing that the RTL code using 8-bit packet which is analyzed by DC is 0.21,Comparative experice tell us that the design circuit is 20% faster than the RTL code in speed.