Design and Optimize Clock Skew for High-speed DDR3 Memory Controller

In this paper, we finish the physical design of DDR3 memory controller in a high-performance and massive data processor chip base on 65 nm process. The paper presented the floorplan and clock tree synthesis of DDR3 memory controller. Due to the biggish bus skew of DDR3 PHY, we recommended the precise manual intervention to clock tree of the critical clock path and made the logical registers optimization. The bus skew of DDR3 PHY was controlled less than 30ps successfully.