Design of Cluster Memory Structure for Reconfigurable Cideo Array Processor

A high efficient and parallel access memory structure is proposed. The architecture adopts the method of "logical sharing, physical distribution" and parallel storage of multiple memory blocks, which realizes the parallel access of 4×4 video array processors. The experimental results show that the proposed architecture can support simultaneous read/write operations of 16 light nuclear processing elements, the highest frequency is 200 MHz, access to the peak bandwidth of 6.25 GB/s. Finally, the 8×8 two-dimensional discrete cosine transform algorithm is mapped and compared. It is found that the cluster memory structure can provide data storage bandwidth of 312.2 Msamples/s. Compared with the same type of array structure, the number of execution cycles decreased 31.67%, frequency doubled, memory bandwidth is increased by 192.60%.