SONG Peng-cheng, ZHANG Chun. Design of High-speed Solid State Drive in FPGA[J]. Microelectronics & Computer, 2017, 34(12): 63-66, 73.
Citation: SONG Peng-cheng, ZHANG Chun. Design of High-speed Solid State Drive in FPGA[J]. Microelectronics & Computer, 2017, 34(12): 63-66, 73.
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Design of High-speed Solid State Drive in FPGA

    Abstract
  • A high-performance solid state drive(SSD) is designed and implemented in the essay. NAND flash chip that obey the standard of ONFI4.0 is used as the storage meida in SSD. SSD communicate with the host through PCIE bus. The control part is implemented based on FPGA. A dual-bus structure and PCIE3.0 IP core are introduced. NAND flash translation layer(FTL) is also described in detail.
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