Design of CDR Based on Behavioral Model Using Verilog-A and Matlab

In accordance with the demand of fast verification of system level and behavioral level about analog integrated circuit, especially the 500 Mb/s clock and data recovery (CDR) circuit used in the receiver of UWB on-body network.The traditional CDR based on Verilog-A has been used to analyze the loop parameters with big random error in ideal condition.However, in this work, the non-ideal factors such as mismatch of magnitude and time between charge up and down current is proposed, which is also modeled by Verilog-A.Meanwhile, the total phase noise of the loop is synthesized by Matlab script.The comparison of circuit level and behavioral level verify the quickly and exactly characteristics of behavioral model, which means they have significant forward-looking directive meaning to circuit design of CDR.