Emulation of Single Event Upsets in SRAM-based FPGA Using Partial Reconfiguration Techniques

An emulation method of single event upsets (SEUs) in SRAM-based FPGA by using partial reconfiguration techniques was presented. According to the characteristics of SEUs in SRAM-based FPGA, a fault injection model was built to emulate incident particles with different Linear Energy Transfer (LET) and Flux. Preliminary quantitative evaluation of hardening-by-design techniques can be done with this method, to enhance the effectiveness and pertinence, and reduce the time of radiation ground-testing which means less cost. A design with Triple Module Redundancy (TMR) based on Virtex-4 FPGA was been evaluated, and the result showed that this method emulated the SEE and the failure rate was reduced with TMR.