Design and Optimization of a DDR3 Memory Controller with Protocol Controller

A DDR3 Memory controller with protocol controller is implemented to efficiently access the off-chip DDR3 memory in a SoC system. Considering the unmatched property between the SoC system level read-write transactions and the DDR3 SDRAM burst access requirement, a memory transaction smoothing mechanism is implemented in the DDR3 memory controller, which makes well use of the protocol controller's DDR3 SDRAM memory command pipeline and can reduce the times of the actual off-chip SDRAM access to improve efficiency of the entire DDR3 memory controller. Verilog model and physical implementation of the memory controller are carried out. Evaluation based on synthetic stimulus show that the smoothing mechanism can improve the efficiency of the DDR3 memory controller.