Low Power Verification Based on Multi-Cores DSP

With the IC design have developed into the nanometer era especially below 65 nm technology,the scale and the frequency of the IC are improved so that the power dissipation has become the main concern after aera and performance.For the IC design concerns with the design power increasing,the verification should be oriented the low power design.This paper presents the knowledges,principles and technologies about the low power design.For the low power technologies,this paper present a high performance and valid low power verification methodology based on SystemVerilog in a Multi-Core DSP chip.