Design of a Single Event Effects Hardened RS Flip-Flops

A novel RS flip-flop is proposed in order to degrade the influence of single event upset and single event transient. The proposed circuit can resist single event upset with the help of dual interlocked cell. Moreover, a guard gate and a Schmitt trigger are employed to be immune to single event transient. The proposed circuit is implemented in a 0.25 μm commercial standard CMOS process. The Spectre simulation results demonstrate that the proposed circuit is immune to the single event upset and single event transient as only one single event happens. Compared with the triple modular redundancy providing same reliability, the die area and power dissipation of the proposed circuit are decreased by 27.8% and 43.1%, respectively.