Research on a SOC Asynchronous Interface of GALS

A low-power system-on-chip (SOC) asynchronous interface in global asynchronous local synchronous (GALS) style, which based on MOUSETRAP asynchronous pipelines architecture, is presented. A transistor-level method is introduced to optimize the circuits' power-performance. A tunable delay mechanism based on multi-delay's power supply is used to improve the process portability of the asynchronous interface circuits. This asynchronous interface architecture can be applied to the multi-supply SOC design of which the high-speed data rate and low-power are mandatory.