Design of a Six-stage Pipelined MIPS Processor Based on FPGA

SUN Qiao-zhi, SHI Hui-bin. Design of a Six-stage Pipelined MIPS Processor Based on FPGA[J]. Microelectronics & Computer, 2015, 32(4): 31-34,39.

Citation:

SUN Qiao-zhi, SHI Hui-bin. Design of a Six-stage Pipelined MIPS Processor Based on FPGA[J]. Microelectronics & Computer, 2015, 32(4): 31-34,39.

Citation:

SUN Qiao-zhi, SHI Hui-bin. Design of a Six-stage Pipelined MIPS Processor Based on FPGA[J]. Microelectronics & Computer, 2015, 32(4): 31-34,39.

Abstract

A 32-bit embedded six-stage pipelined processor is designed in this paper, which is compatible with MIPS instruction set. The six stages make the task of each stage balanced. The solutions to data hazards and control hazards in detail are given out. The processor is implemented in FPGA, and its clock frequency can be up to 81.7 MHz in DE2 development board. The comprehensive results of the design are presented, and the software simulation and hardware verification results prove the correctness of the design.

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