Design and research of task management mechanism based on RISC-V heterogeneous system

With the rapid development of design for specific fields' accelerator, heterogeneous system based on accelerator is a new trend of computing architecture design. However, the complex heterogeneous system challenges the programming mode and the efficient interaction between processor and accelerator. How to describe the computing tasks between the main processor and the accelerator, and how to reduce the cost of data transmission between them, and how to make the processor efficiently complete the task management and scheduling of the accelerator are the key technology to ensure the performance of heterogeneous systems. Based on a reconfigurable array driven by data flow, this paper proposes a task management mechanism and interconnection mode with the master controller by abstracting its driving mode, data flow direction, input and output, including the host interface of hardware, task management system of software, etc., which is implemented and verified on Rocket Core based on risc-v instruction.