A General Loop-Compiling Technique for Course-Grained Reconfigurable Processor

Coarse-grained reconfigurable processor combines the advantages of high performance and high flexibility, but the existing compiler technology is difficult to deal with variable-length loops and imperfect loops. In this paper, we propose an efficient compilation technique for variable-length loops and imperfect loops, so that the compiler can deal with the general form of loops and can make full use of the reconfigurable processor computing power.