Establishment of CAN Bus Protocol Verification Model Using Verilog

With increasing difficulty of the integrated circuit chip design, verification has become increasingly complex, fully capable of comprehensive verification, shorten the development cycle, reduce design cost are becoming particularly important issues for validators. This article is based on Verilog HDL to design a CAN bus verification model to validate CAN bus nodes. In order to meet the needs of the verification, capabilities of error injection and user interface are added, these functions simplify the complexity of the test platform. Finally, the integrity test of the DUT’s CAN protocol within bus model is achieved. Our analysis of typical examples verify the effectiveness of the method.