Reconfigurable Array Processor Harris Algorithm is Implemented in Parallel

In this paper, the reconfigurable array processor Harris parallelization algorithm mapping methods, the reconfigurable array processor solves the algorithm on the hardware modification requires the defect of structure readjustment between cluster parallel at the same time solve the defect of the algorithm in software speed and time delay.By modelsim, Xilinx ISE company hardware design tools and BEE4 development platform to realize the Harris algorithm to the resolution of 512 * 512 image map, the experiment results show that the algorithm mapping time of 0.143 ms, under the condition of the time compared to the same CPU, GPU, the FPGA implementation Harris algorithm mapping time is short.