ZHU Xue-liang, CHAI Zhi-lei, ZHONG Chuan-jie, ZHANG Ping. Design and Implemenation of FPGA-based Convolution IP Core for Image Processing[J]. Microelectronics & Computer, 2011, 28(6): 188-192.
Citation: ZHU Xue-liang, CHAI Zhi-lei, ZHONG Chuan-jie, ZHANG Ping. Design and Implemenation of FPGA-based Convolution IP Core for Image Processing[J]. Microelectronics & Computer, 2011, 28(6): 188-192.

Design and Implemenation of FPGA-based Convolution IP Core for Image Processing

  • We present a new 2-D convolution IP core for real-time image processing taking advantage of the feature of convolution.Thanks to FPGA′s parallel structure and rich memory resource this design does well in modularity and expandability and the convolution′s window size and cofficients can be changed flexibly.Beside satisfying practical applications the new IP tries it′s best to save hardware.It makes convolution more flexible and convenient.
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