Research and Design of High PSR,Low power,Chip-level LDO

In order to reduce the input voltage noise while supplying a stable output voltage and integrate on-chip,a kind of new CMOS,chip-level LDO is proposed in this paper.One of the most notable features is that its quiescent current is quite low.With the 3.3Vpower supply,the quiescent current is only 10μA.So the power consumption is considerable for chip-level.Meanwhile,the power supply rejection (PSR) is also promoted with an effective PSR improved method,which can reach-45dB in low frequency and the worst case can also reach around-20dB.So it can better reject the power supply noise at the output and is suitable for noise-sensitive circuits.