An All-Digital Clock Generator Using Relative Delay Ratio Modeling

Using the relative delay ratio modeling, an all-digital clock generator which is used for low power applications is proposed. It overcomes the effects of process, voltage and temperature (PVT) variations. The clock generator is composed of delay ratio evaluator, mapper block and digitally controlled oscillator. A 10~40MHz adjustable clock generator is implemented in smic 180nm CMOS technology with 1.02mm² (excluding IO pad). The measured results show that the worst output frequency error is less than 3% at 25MHz, with 1.6~2V supply voltage, 0~80℃ temperature variation. The phase noise of output clock is -114.82dBc/Hz at 1MHz offset with high stability performance.