High level synthesis impementation of rate compatible IDPC decoder

Aiming at the problem of high complexity and long development cycle of Low-Density Parity-Check (LDPC) code decoding algorithm, a high-level synthesis method is proposed to realize the hardware design effectively. The purpose of this paper is to realize the hardware implementation of code-rate-compatible QC-LDPC decoding algorithm. Firstly, the structure of the algorithm is described by using C language. Secondly, the algorithm is adjusted and optimized from the data storage and cyclic scheduling in the code to adapt to the hardware surroundings. And then use the high-level synthesis tool to further constrain the algorithm behavior in interface synthesis, loop optimization, array optimization and so on, and improve the resource utilization rate and data throughput rate of the decoding module. Finally, through the RTL level description of C integrated algorithm, a variety of optimization schemes are comparatively analyzed to deeply understand the high-level comprehensive implementation details of LDPC code decoding algorithm. The results of co-simulation show that using high-level synthesis tools to achieve LDPC decoder in the greatly shorten the development cycle, still has better decoding performance.