Single Channel Frequency Domain Anti-Jamming Algorithm and FPGA Implementation

In order to decrease the resource consumption and practice cost on the implementation of frequency domain anti-jamming algorithm, the principle of traditional two channels frequency domain narrow band interference rejection algorithm are analyzed. Thealgorithm adds a process of data access. The input data is reused to achieve the traditional two channels interference rejection. This way optimizes signal processing flow and reduce the amount of calculation. Finally, algorithm is established in the field programmable gate array. For the purpose of not raising the requirement of clocking frequency in the implementation, the dedicated data access module is designed to export odd-even data individually and paralleled butterfly operation unit of Fourier transform module is also customized. Improved hardware structure not only can reduce power dissipation but also is a half less than traditional two channels implement method in the storage resource. Therefore, the algorithm and implement method proposed in the paper can realize in the low -configure FPGA and lower the hardware cost immensely.