Design of a High Speed and Low Dissipation Drive Circuit in Power Factor Correction Circuit

In Power Factor Correction Circuit,the gate drive circuit should have high converting speed and low power consumption.To meet the requirements,we have modified the old push_pull circuit and finally design a new gate drive circuit using a simple level_shift circuit.Based on 0.35 μm BCD process,using Hspice simulation tools,the result shows that at the conditions of 17 V supply,4.7 nF load capacitor and 65 kHz fixed switching frequency,the rise time of drive pulse is 25 ns from 2~12 V,the fall time is 35 ns from 12~2 V,the power loss is 24.3 mW and 13.1 mW with high voltage transistor on and off respectively,this finally verifies the effectiveness of the design.