LV Jian, LI Hua, ZHOU Yun, WANG Lu-xia, JIANG Ya-dong. High Performance CMOS Sample and Hold Circuit[J]. Microelectronics & Computer, 2010, 27(3): 140-143,147.
Citation:
LV Jian, LI Hua, ZHOU Yun, WANG Lu-xia, JIANG Ya-dong. High Performance CMOS Sample and Hold Circuit[J]. Microelectronics & Computer, 2010, 27(3): 140-143,147.
LV Jian, LI Hua, ZHOU Yun, WANG Lu-xia, JIANG Ya-dong. High Performance CMOS Sample and Hold Circuit[J]. Microelectronics & Computer, 2010, 27(3): 140-143,147.
Citation:
LV Jian, LI Hua, ZHOU Yun, WANG Lu-xia, JIANG Ya-dong. High Performance CMOS Sample and Hold Circuit[J]. Microelectronics & Computer, 2010, 27(3): 140-143,147.
A high linearity, high resolution and high speed sample/hold circuit is proposed.A novel low distortion switch is proposed, which is composed of four PMOS transistors, one capacitor and one NMOS switch.It can directly sample a bipolar signal and increase the sampling linearity with low noise and distortion.This circuit achieves a 120dB SFDR when sampling a 1V peak-to-peak, 156kHz bipolar signal under 10MS/s sampling rate.
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