A Novel and High Performance SEU/SET-tolerant Latch Design

Along with the advance of process technology,the susceptibility of integrated circuit to single event effect has been increasing.Therefore,to design the circuits which can tolerate SEE become more and more important.This paper presents a novel harden latch which can mitigate the effect of SEE to IC chips.It is based on a mixed structure of DICE and C element,and utilizes the Dual Modular Redundancy (DMR) technology.Simulations using Hspice demonstrate that the structure proposed in this paper has a excellent performance to tolerate SEU/SET,and its soft error rate is 44.9% less than the feedback and redundant design proposed by M.Fazeli.Besides,compare to traditional Triple Modular Redundancy (TMR),the proposed latch consumes about 28.6% less area,and more than47% power is saved.