WU Yong-jun, ZHENG Hong-chao, LI Zhe, ZHAO Xu. Research on integrated circuit SEU simulation technology based on masking factor algorithm[J]. Microelectronics & Computer, 2020, 37(8): 61-65.
Citation: WU Yong-jun, ZHENG Hong-chao, LI Zhe, ZHAO Xu. Research on integrated circuit SEU simulation technology based on masking factor algorithm[J]. Microelectronics & Computer, 2020, 37(8): 61-65.

Research on integrated circuit SEU simulation technology based on masking factor algorithm

  • By analyzing the characterization form and propagation law of single event effect for integrated circuit, this paper establishes a set of SEE simulation and evaluation method which has the advantages of scientific and reasonable, simple operation. Based on the research of integrated circuit SEE masking factor calculation method and simulation evaluation process, the SEE masking factor calculation method and simulation software based on fault injection method are designed. In this paper, a 65nm CMOS bulk silicon process ASIC circuit is simulated in software by using this simulation method. The analysis of the software simulation and SEE test results show that the simulation method can be used for SEE simulation of large-scale integrated circuits and it has certain predictive ability for SEE test results.
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