A Method of Verification Cortex-M0 IP Core by Using FPGA

According to the advanced high performance bus (AHP) interface protocol, the synthesizable RTL code of the 32/16 bit memory and I/O interface is designed. The RTL code replaces the behavior-level memory interface code of in cortex_m0_designstart. The method can build a complete embedded system in FPGA which has the function of memory and I/O architecture to meet the demand for rapid system level function verification using Cortex-M0 IP. The design method is provided in this paper, and the RTL code is verified on Altera's EP3C40 also. The designed hardware system occupies about 7688 logical unit and 17408bits memory cell.