Efficient Implementation of Parallel AES Algorithm Encryption and Decryption Circuit

The basic principles of AES algorithm is introduced in this paper. In order to share the same round operation in encryption and decryption process, an equivalent round operation structure is employed based on the structural characteristics of the algorithm. A general circuit structure of AES algorithm is designed by using iteration method, decided whether to work as encryption or decryption by control signal. The whole encryption and decryption system circuit is composed of 6 AES algorithm cores in parallel to increase throughput. The simulation result shows the clock frequency is 177.9 MHz and the throughput achieves 5.69 Gb/s.