Simulation and Evaluation of SEU Effects in SRAM-based FPGA with Random Fault Injection

In space applications, the SRAM-based FPGA circuitry suffers from the logical bit flipping error caused by single event effects (SEU). In the design process, In order to evaluate the capability of fault tolerance for functional circuits, a method of random multi bit fault injection and statistical evaluation based on partial reconfiguration technique is proposed to compute the dynamic cross section. A fault injection system is built, and the six channel shift register is used as the functional circuit to perform the random fault injection test with multiple parameter combinations (number of repetitions and injection bits). The experimental data are compared with the traditional methods, and the feasibility and accuracy of the method described in this paper are proved.